1. Field of the Invention
Embodiments in accordance with the present disclosure are directed to integrated circuits containing non-volatile memory cell arrays and particularly those arrays incorporating passive element memory cells.
2. Description of the Related Art
Materials having a detectable level of change in state, such as a resistance or phase change, are used to form various types of non-volatile semiconductor based memory devices. For example, simple antifuses are used for binary data storage in one time field-programmable (OTP) memory arrays by assigning a lower resistance initial physical state of a memory cell to a first logical state such as logical ‘0,’ and assigning a higher resistance physical state of the cell to a second logical state such as logical ‘1.’ Some materials can have their resistance switched back in the direction of their initial resistance. These types of materials can be used to form re-writable memory cells. Multiple levels of detectable resistance in materials can further be used to form multi-state devices which may or may not be re-writable.
Materials having a memory effect such as a detectable level of resistance are often placed in series with a steering element to form a memory cell. Diodes or other devices having a non-linear conduction current are typically used as the steering element. The memory effect of the cell is often referred to as the state change element. In many implementations, a set of word lines and bit lines are arranged in a substantially perpendicular configuration with a memory cell at the intersection of each word line and bit line. Two-terminal memory cells can be constructed at the intersections with one terminal (e.g., terminal portion of the cell or separate layer of the cell) in contact with the conductor forming the respective word line and another terminal in contactor with the conductor forming the respective bit line. Such cells are sometimes referred to as passive element memory cells.
Two-terminal memory cells with resistive state change elements have been used in three-dimensional field programmable non-volatile memory arrays because of their more simple design when compared to other three-terminal memory devices such as flash EEPROM. Three-dimensional non-volatile memory arrays are attractive because of their potential to greatly increase the number of memory cells that can be fabricated in a given wafer area. In three-dimensional memories, multiple levels of memory cells can be fabricated above a substrate, without intervening substrate layers. One type of three-dimensional memory includes pillars of layers formed at the intersection of upper and lower conductors. The pillars can take on various configurations, including a steering element such as a diode in series with a state change element such as an antifuse or other state change material in one example.
The formation of pillar structures often includes etching a first plurality of layers into strips in a first direction, filling the gaps between strips with a dielectric material, depositing a second plurality of layers, and then etching both plurality of layers in a second direction orthogonal to the first. The formation of these pillar structures can include a number of fabrication processes that require precise alignment in forming the small feature sizes of the structures. These processes can present a range of difficulties. For example, the second etch process is typically selective so as not to etch the dielectric fill material. This can sometimes lead to the inadvertent shorting of adjacent structures due to stringers formed from a portion of material trapped under the dielectric and not removed by the second etch.
There remains a need for improved pillar designs and corresponding fabrication processes for forming the same in non-volatile memory array technologies.